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| hardware:jtag 2008/08/17 01:53 | hardware:jtag 2017/09/06 18:38 current | ||
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| Line 13: | Line 13: | ||
| * You need a JTAG cable | * You need a JTAG cable | ||
| - | ===== JTAG Interface scheme for DNS-323 ===== | + | Two types of jtag cables are discussed here: |
| + | 1: The "Wiggler" style, which is basically a conversion between the jtag interface on the embedded system and the parralel (printer) port on your PC. | ||
| + | 2: The "Amontec JTAGKey Tiny" (other commercially models may or may not work), which provides a USB connection at the PC side. | ||
| + | Comparison: pro method 1: cheaper, Pro method 2: less soldering (faster?) | ||
| - | {{hardware:dns-323-jtag.pdf| JTAG Port Pinout and Wiggler style Programmer}} | ||
| - | |||
| - | |||
| - | ==== Amontec JTAGKey Tiny ==== | ||
| - | [http://www.amontec.com/jtagkey-tiny.shtml| JTAGKey Tiny] | ||
| - | |||
| - | Solder 4K7 Ohm resistors @ R202 R201 R200 | ||
| - | Connect JTAG pins just like the Wrigler port, and also bridge R199 (EN pin to VCC) to enable JTAG. | ||
| - | |||
| - | openocd.cfg: | ||
| - | |||
| - | <code> | ||
| - | telnet_port 4444 | ||
| - | gdb_port 3333 | ||
| - | |||
| - | interface ft2232 | ||
| - | ft2232_device_desc "Amontec JTAGkey" | ||
| - | ft2232_layout jtagkey | ||
| - | ft2232_vid_pid 0x0403 0xcff8 | ||
| - | jtag_speed 3 | ||
| - | |||
| - | reset_config srst_only | ||
| - | jtag_device 4 0x1 0xf 0xe | ||
| - | |||
| - | jtag_nsrst_delay 1200 | ||
| - | jtag_ntrst_delay 1200 | ||
| - | |||
| - | #target configuration | ||
| - | daemon_startup reset | ||
| - | |||
| - | #target <type> <endianness> <startup mode> <chainpos> <variant> | ||
| - | target feroceon little run_and_halt 0 | ||
| - | run_and_halt_time 0 500 | ||
| - | |||
| - | # planing with flash code - work in progress | ||
| - | #working_area 0 0x00400000 0x40000 nobackup | ||
| - | |||
| - | # driver addr size chip_width bus_width options | ||
| - | flash bank cfi 0xff800000 0x800000 1 2 0 | ||
| - | |||
| - | </code> | ||
| ===== JTAG Pinout Reference ===== | ===== JTAG Pinout Reference ===== | ||
| Line 70: | Line 32: | ||
| **Note nTRST must be sent a buffered high signal to use JTAG** | **Note nTRST must be sent a buffered high signal to use JTAG** | ||
| + | Be aware that this pinout seems to be based on the DNS 323 version B2 and the CH3SNAS. The DNS-323 version A1 has the same space for a header, but the location of the surrounding resistors is different. This might or might not have consequences for the validity of the pinout as above. (Anyone: more information on the A1 rev.?) | ||
| + | Rev A1 is the same pinout, smd resistors are already attached, just add header. | ||
| - | ===== OpenOCD ===== | ||
| - | ==== openocd.cfg ==== | + | |
| + | ===== JTAG Interface scheme for DNS-323 with the Wiggler port===== | ||
| + | See the attached pinout: | ||
| + | {{:hardware:dns-323-jtag.png}} | ||
| + | |||
| + | |||
| + | |||
| + | ==== openocd configuration file for the Wiggler method ==== | ||
| + | |||
| + | openocd.cfg | ||
| <code> | <code> | ||
| cat openocd.cfg | cat openocd.cfg | ||
| Line 114: | Line 86: | ||
| halt | halt | ||
| </code> | </code> | ||
| + | |||
| + | |||
| + | ===== JTAG Interface scheme for DNS-323 with the Amontec JTAGKey Tiny ===== | ||
| + | [[http://www.amontec.com/jtagkey-tiny.shtml| JTAGKey Tiny]] | ||
| + | |||
| + | Solder 47 KOhm resistors @ R202 R201 R200 | ||
| + | Connect JTAG pins just like the Wiggler port, and also bridge R199 (EN pin to VCC) to enable JTAG. | ||
| + | Refer to the top half of the pdf as attached in the previous section. | ||
| + | Pinout of the jtagkey tiny is available [[http://www.amontec.com/jtag_pinout.shtml| here]] | ||
| + | |||
| + | ==== openocd configuration file for the Amontec JTAGKey Tiny ==== | ||
| + | |||
| + | openocd.cfg | ||
| + | <code> | ||
| + | telnet_port 4444 | ||
| + | gdb_port 3333 | ||
| + | |||
| + | interface ft2232 | ||
| + | ft2232_device_desc "Amontec JTAGkey" | ||
| + | ft2232_layout jtagkey | ||
| + | ft2232_vid_pid 0x0403 0xcff8 | ||
| + | jtag_speed 3 | ||
| + | |||
| + | reset_config srst_only | ||
| + | jtag_device 4 0x1 0xf 0xe | ||
| + | |||
| + | jtag_nsrst_delay 1200 | ||
| + | jtag_ntrst_delay 1200 | ||
| + | |||
| + | #target <type> <endianness> <chainpos> <variant> | ||
| + | target feroceon little 0 | ||
| + | |||
| + | # planing with flash code - work in progress | ||
| + | #working_area 0 0x00400000 0x40000 nobackup | ||
| + | |||
| + | # driver addr size chip_width bus_width options | ||
| + | flash bank cfi 0xff800000 0x800000 1 2 0 | ||
| + | |||
| + | #target configuration | ||
| + | init | ||
| + | reset run | ||
| + | sleep 500 | ||
| + | halt | ||
| + | |||
| + | </code> | ||
| + | |||
| + | |||
| + | ===== OpenOCD ===== | ||
| + | |||
| ==== Running OpenOCD ==== | ==== Running OpenOCD ==== | ||
| Line 150: | Line 171: | ||
| </code> | </code> | ||
| - | ===== TODO ====== | + | ===== TODO ===== |
| * The flash code in OPENOCD does not understand CFI mode 2 access. However this looks to be easy to fix. There is an early patch that attempted to address this but was never added into the project release. This code provides a good starting point. | * The flash code in OPENOCD does not understand CFI mode 2 access. However this looks to be easy to fix. There is an early patch that attempted to address this but was never added into the project release. This code provides a good starting point. | ||
| ===== Links ===== | ===== Links ===== | ||
| - | * [[http://forum.dsmg600.info/t250-DNS323-JTAG-Pinout-interface-details.html|Forum thread]] | + | * [[http://dns323.kood.org/forum/t250-DNS323-JTAG-Pinout-interface-details.html|Forum thread]] |
